library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown is
port( clk50m,rst,key:in std_logic;
dig:out std_logic_vector(4 downto 1);
seg:out std_logic_vector(6 downto 0);
led:out std_logic
);
end countdown;
architecture ach of countdown is
component countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer ;
cout:out std_logic
);
end component;
component freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end component;
component mypll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT std_logic;
locked : OUT STD_LOGIC
);
END component;
component cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end component;
component ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end component;
signal clk1m,clk1k,clk1s,locked:std_logic;
signal qh,ql:integer;
signal qcnt,qshow:integer;
begin
u0:mypll port map(not rst,clk50m,clk1m,locked);
u1:freqn generic map(1000000)
port map(clk1m,locked,clk1s);
u2:freqn generic map(1000)
port map(clk1m,locked,clk1k);
u3:cd port map(clk1s,key,qh,ql);
u4:countn generic map(4)
port map(clk1k,locked,'1',qcnt);
qshow<=qh when qcnt=1 else
ql when qcnt=0 else
10;
dig<="1110"when qcnt=0 else
"1101" when qcnt=1 else
"1111";
u5:ledshow port map(qshow,seg);
led<='0' when qh=0 and ql=0 else
'1';
end ach;
library ieee;
use ieee.std_logic_1164.all;
entity cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end cd;
architecture ach of cd is
begin
process(clk,rst)
begin
if rst='0' then
qh<=6;
ql<=0;
elsif rising_edge(clk) then
if ql=0 then
ql<=9;
if qh=0 then
qh<=0;
ql<=0;
else
qh<=qh-1;
end if;
else
ql<=ql-1;
end if;
end if;
end process;
end ach;
--input number 0~9, and output abcdefg for digital tube
library ieee;
use ieee.std_logic_1164.all;
entity ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end ledShow;
architecture ach of ledShow is
begin
with q select
seg<="1000000" when 0 ,
"1111001" when 1 ,
"0100100"when 2 ,
"0110000"when 3 ,
"0011001"when 4 ,
"0010010"when 5 ,
"0000010"when 6 ,
"1111000"when 7 ,
"0000000"when 8 ,
"0010000" when 9 ,
"1111111" when others;
end ach;
--任意整数分频
library ieee;
use ieee.std_logic_1164.all;
--实体
entity freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end freqN;
--结构体
architecture ach of freqN is
--任意进制计数器元件例化声明
component countN
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
cout:out std_logic;
qdata:out integer
);
end component;
signal qdata:integer:=0;
signal cout:std_logic;
begin
--n进制计数器例化
u0:countN generic map(n)
port map(clk,rst,'1',open,qdata);
--clkout<='1' when qdata--'0';
process(rst,clk)
begin
if rst='0' then
clkout<='0';
elsif rising_edge(clk) then
if qdata=0 then
clkout<='0';
else
clkout<='1';
end if;
end if;
end process;
end ach;
library ieee;
use ieee.std_logic_1164.all;
--实体任意进制计数器
entity countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer;
cout:out std_logic
);
end countN;
--结构体
architecture ach of countN is
--任意进制计数器元件例化声明
signal qtmp:integer:=0;
begin
process(rst,clk) --敏感信号
begin
if rst='0' then
qtmp<=0;
cout<='0';
elsif rising_edge(clk) then
if en='1' then
if qtmp=n-1 then
qtmp<=0;
else
qtmp<=qtmp+1;
end if;
if qtmp=n-2 then
cout<='1';
else
cout<='0';
end if;
end if;
end if;
-- if qtmp=n-1 then
--cout<='1';
-- else
--cout<='0';
-- end;
end process;
qdata<=qtmp;
end ach;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown is
port( clk50m,rst,key:in std_logic;
dig:out std_logic_vector(4 downto 1);
seg:out std_logic_vector(6 downto 0);
led:out std_logic
);
end countdown;
architecture ach of countdown is
component countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer ;
cout:out std_logic
);
end component;
component freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end component;
component mypll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT std_logic;
locked : OUT STD_LOGIC
);
END component;
component cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end component;
component ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end component;
signal clk1m,clk1k,clk1s,locked:std_logic;
signal qh,ql:integer;
signal qcnt,qshow:integer;
begin
u0:mypll port map(not rst,clk50m,clk1m,locked);
u1:freqn generic map(1000000)
port map(clk1m,locked,clk1s);
u2:freqn generic map(1000)
port map(clk1m,locked,clk1k);
u3:cd port map(clk1s,key,qh,ql);
u4:countn generic map(4)
port map(clk1k,locked,'1',qcnt);
qshow<=qh when qcnt=1 else
ql when qcnt=0 else
10;
dig<="1110"when qcnt=0 else
"1101" when qcnt=1 else
"1111";
u5:ledshow port map(qshow,seg);
led<='0' when qh=0 and ql=0 else
'1';
end ach;
library ieee;
use ieee.std_logic_1164.all;
entity cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end cd;
architecture ach of cd is
begin
process(clk,rst)
begin
if rst='0' then
qh<=6;
ql<=0;
elsif rising_edge(clk) then
if ql=0 then
ql<=9;
if qh=0 then
qh<=0;
ql<=0;
else
qh<=qh-1;
end if;
else
ql<=ql-1;
end if;
end if;
end process;
end ach;
--input number 0~9, and output abcdefg for digital tube
library ieee;
use ieee.std_logic_1164.all;
entity ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end ledShow;
architecture ach of ledShow is
begin
with q select
seg<="1000000" when 0 ,
"1111001" when 1 ,
"0100100"when 2 ,
"0110000"when 3 ,
"0011001"when 4 ,
"0010010"when 5 ,
"0000010"when 6 ,
"1111000"when 7 ,
"0000000"when 8 ,
"0010000" when 9 ,
"1111111" when others;
end ach;
--任意整数分频
library ieee;
use ieee.std_logic_1164.all;
--实体
entity freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end freqN;
--结构体
architecture ach of freqN is
--任意进制计数器元件例化声明
component countN
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
cout:out std_logic;
qdata:out integer
);
end component;
signal qdata:integer:=0;
signal cout:std_logic;
begin
--n进制计数器例化
u0:countN generic map(n)
port map(clk,rst,'1',open,qdata);
--clkout<='1' when qdata
process(rst,clk)
begin
if rst='0' then
clkout<='0';
elsif rising_edge(clk) then
if qdata=0 then
clkout<='0';
else
clkout<='1';
end if;
end if;
end process;
end ach;
library ieee;
use ieee.std_logic_1164.all;
--实体任意进制计数器
entity countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer;
cout:out std_logic
);
end countN;
--结构体
architecture ach of countN is
--任意进制计数器元件例化声明
signal qtmp:integer:=0;
begin
process(rst,clk) --敏感信号
begin
if rst='0' then
qtmp<=0;
cout<='0';
elsif rising_edge(clk) then
if en='1' then
if qtmp=n-1 then
qtmp<=0;
else
qtmp<=qtmp+1;
end if;
if qtmp=n-2 then
cout<='1';
else
cout<='0';
end if;
end if;
end if;
-- if qtmp=n-1 then
--cout<='1';
-- else
--cout<='0';
-- end;
end process;
qdata<=qtmp;
end ach;
艾达对川木：
You only see what ur eyes want to see
How can life be what u want it to be？
You r frozen when your heart's not open
You r so consumed with how much u get
You waste your time with hate and regret
You r broken when your heart's not open
Now there's no point in placing the blame
And u should know I'd suffer the same
If I lose u, my heart will be broken
Love is a bird, she needs to fly, let all the hurt inside you die
You r frozen when ur heart's not open.
If I could melt ur heart, we'd never be apart.
Give yourself to me, u r the key.
You only see what ur eyes want to see
How can life be what u want it to be？
You r frozen when your heart's not open
You r so consumed with how much u get
You waste your time with hate and regret
You r broken when your heart's not open
Now there's no point in placing the blame
And u should know I'd suffer the same
If I lose u, my heart will be broken
Love is a bird, she needs to fly, let all the hurt inside you die
You r frozen when ur heart's not open.
If I could melt ur heart, we'd never be apart.
Give yourself to me, u r the key.
ROAD TO WEMBLEY TOUR 2023 ️ the good witch is getting her own yellow brick road this uk tour has been such a dream and now we get to do it again in october the very season of the witch herself and the album will be out and i will get to hear from all the ppl in my heart once again <3333 if u preorder the album u will get a special presale code next week before general sale starts this friday i literally cannot wait :’)
#maisiepeters##MaisiePeters[超话]#
#maisiepeters##MaisiePeters[超话]#
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